Track Record

Engineering Experience

Research and Outreach Head

Students Society of ECE

Aug 2026 – Present (3 mos) | Chennai - On-site

Intern (Edge AI & Embedded Vision)

e-con Systems

Apr 2026 – Nov 2026 (7 mos) | Chennai - Hybrid

Engineered a container-free native Linux runtime port of Google’s mobile vision engine for x86_64 and ARM64 platforms via a custom Bionic-to-glibc translation shim.
Developed high-throughput, zero-copy C++ and Python SDKs interfacing multi-camera V4L2 video streams directly with embedded neural network backends.
Trained, pruned, and fine-tuned edge vision models using PyTorch; executed post-training quantization (INT8/FP16) and deployed optimized pipelines across TensorRT for NVIDIA Jetson and TFLite for edge devices.

Research Intern (FPGA & Systems)

Directorate of Research, SRM Group

Mar 2026 – Present (8 mos) | Chennai - On-site

Developed custom hardware accelerators and compute pipelines using Verilog, VHDL, and Vivado HLS across Xilinx Zynq and Microchip PolarFire FPGA architectures.
Ran cycle-accurate RTL verification, testbench simulation, and corner-case functional debug using Vivado, GHDL, and ModelSim.
Integrated and evaluated on-chip bus interconnects and protocols, handling AXI4-Lite, AXI-Stream, AXI-DMA, and Wishbone interfaces.
Built bare-metal C/C++ runtimes and TFLite Micro inference engines on ARM Cortex-M microcontrollers, implementing static memory arena management.

Lead Architect & Researcher

The Silis Foundation

Jan 2026 – Present (10 mos) | Open Hardware & Silicon Research

Founded and lead open-source silicon and digital design research under The Silis Foundation, advancing accessible ASIC infrastructure and empirical microarchitectural exploration.
Architected the Silis RTL-to-GDSII IDE, unifying synthesis, place-and-route, timing analysis, and DRC/GDS engines (Yosys, OpenROAD, OpenSTA, Magic) with native C++ DEF parsing engines bound via pybind11.
Conduct digital design research and microarchitectural comparisons—benchmarking spatial compute fabrics (such as systolic tensor arrays), custom RISC-V coprocessor extensions (GEMMrv32), and bare-metal runtime infrastructures for open silicon.

Student's Council President

Holy Cross Matriculation HSS

Jul 2023 – May 2024 (11 mos) | Chennai

Student's Council Vice-President

Holy Cross Matriculation HSS

Jul 2022 – May 2023 (11 mos) | Chennai

Verified Silicon & Hardware Implementations

Featured Projects

Silis: RTL-to-GDSII IDE GitHub ↗

Modular ASIC design environment integrating Yosys, OpenROAD, OpenSTA, and Magic VLSI. Features native C++ DEF parsing engines bound via pybind11 to render chip layouts at 60 FPS.

Technical Architecture & Implementation

My flagship open-source silicon project under The Silis Foundation. Built to replace fragmented EDA toolchains with a clean, deterministic physical chip design environment:

Unified Synthesis-to-Physical Plane: Automated orchestration of Yosys logic synthesis, OpenROAD placement & routing, OpenSTA static timing analysis, and Magic VLSI DRC verification.
Hardware Acceleration Engine: Engineered a native C++ backend parser bound via pybind11 for sub-millisecond DEF layout decoding, multi-million gate layout virtualization, and real-time clock-tree visualization.
Focus: Open-source silicon toolchain democratization, from RTL directly to verified GDSII.

Automated RTL→GDSII Flow · Zero-Friction Open-Source Tapeout

C++17/20 PyQt6 OpenROAD Yosys

GEMMrv32 (RISC-V Coprocessor) GitHub ↗

Spatial 8x8 systolic-array matrix multiplier integrated directly into the NEORV32 RISC-V processor Custom Functions Subsystem (CFS) with local ping-pong data tiling registers.

Technical Architecture & Implementation

Custom digital coprocessor architecture for embedded RISC-V compute engines:

Systolic Compute Grid: 64 Processing Elements (PEs) organized in an 8×8 2D systolic grid running cycle-accurate matrix multiplication directly inside processor register space.
CFS Integration: Tightly coupled into the NEORV32 core pipeline using custom instruction triggers and double-buffered internal ping-pong registers.
Performance Footprint: 26.2× speedup over compiler-optimized (GCC -O3) RV32 software matrix multiplication loops.

64 PEs · 26.2x faster than GCC -O3 loop-unrolled baseline on RV32

VHDL RISC-V GHDL HW/SW Co-Design

PulseGEMM (PolarFire SoC) GitHub ↗

Layer-wise 16x16 INT8 systolic compute engine optimized for the Microchip PolarFire SoC. Integrated with a 64-bit AXI4 master DMA engine with ping-pong SRAM buffering for zero-copy 2D strided activation extraction.

Technical Architecture & Implementation

High-throughput digital accelerator core tailored for ultra-low power Microchip PolarFire FPGA silicon:

Compute Peak: 16×16 spatial systolic PE engine delivering 256 MACs/cycle @ 100 MHz, utilizing 256 physical Math Blocks (87.7% DSP utilization).
DMA & Memory Fabric: 64-bit AXI4 master DMA interface with double-buffered on-chip SRAM for seamless compute and data-movement overlap.
Linux Subsystem: Userspace I/O (UIO) kernel interface enabling zero-copy userspace memory mapping without kernel driver switching overhead.
End-to-End Speedup: 51.58× inference acceleration across ResNet-50 convolution workloads compared to dual-core 64-bit RISC-V CPU baselines.

256 MACs/cyc @ 100 MHz · 256 DSPs (87.7%) · 51.58x ResNet-50 speedup

Verilog PolarFire AXI4-DMA /dev/mem

DOOM on GEMMrv32 GitHub ↗

Bare-metal port of the classic DOOM engine targeted to the custom GEMMrv32 RISC-V processor architecture, offloading geometric transformation pipelines to hardware.

Technical Architecture & Implementation

Bare-metal OS-less deployment of id Software's DOOM on custom RISC-V silicon:

Hardware Acceleration of 3D Math: Direct offloading of vertex projections, BSP traversal calculations, and fixed-point matrix rotations to the GEMMrv32 systolic coprocessor.
Bare-Metal Firmware Stack: Custom low-level boot code, deterministic interrupt handlers, and custom framebuffer driver written from scratch without POSIX or OS runtimes.

Bare-Metal RISC-V · Hardware Matrix Transformations · Real-time Rendering

C RISC-V Bare Metal FPGA

GEMMrvStudio GitHub ↗

Developer and simulation IDE for GEMMrv32 coprocessor workflows, providing hardware simulation telemetry, register monitoring, and automated profiling tools.

Technical Architecture & Implementation

Dedicated simulation and coprocessor debugging workbench:

Hardware Telemetry: Cycle-accurate register inspection, execution waveform parsing, and stall-cycle analysis for NEORV32 CFS modules.
Profiling Infrastructure: Visual verification of matrix multiplication outputs against golden Python/NumPy matrix models.

Telemetry & Waveform Profiling · Interactive Coprocessor Debugging

Python GUI RISC-V Simulation

Binarized-YOLO on PYNQ GitHub ↗

Hardware-accelerated 1-bit weight, 3-bit activation Tinier-YOLO CNN overlay on Xilinx Zynq-7000. Replaces multiplier DSPs with raw XNOR-popcount logic gates via Vivado HLS streaming cores.

Technical Architecture & Implementation

Extreme quantization deep-learning accelerator overlay:

XNOR-Popcount Logic: Entire convolution layers calculated using Boolean XNOR gates and popcount bit-counters instead of hardware DSP multipliers.
AXI-Stream Pipeline: Streaming DMA transfers feeding pipelined Vivado HLS compute kernels at ~150× speedup compared to standalone ARM Cortex-A9 execution.

~150x speed multiplier over ARM CPU · Modernized pynq.allocate DMA

Vivado HLS PYNQ-Z2 BNN AXI-Stream

tinyml-rt-pico GitHub ↗

Bare-metal AI execution framework for RP2040 microcontrollers decoupling neural network models from firmware. Streams .tflite weights and pipelines on-demand from SPI SD cards into static memory arenas.

Technical Architecture & Implementation

Zero-heap bare-metal edge AI runtime for microcontrollers:

Firmware-Model Decoupling: Models loaded dynamically from external SPI flash/SD storage into a deterministic static RAM arena without reflashing microcontroller firmware.
Memory Engineering: Operates strictly within the RP2040's 264 KB SRAM envelope with zero heap fragmentation.

Deterministic zero-heap arena · Multi-model hot swapping in 264KB SRAM

C/C++ RP2040 TFLite Micro FatFS

mlkit-barcode-linux GitHub ↗

Container-free Linux translation shim running Google ML Kit's proprietary engine directly on Ubuntu and NVIDIA Jetson without virtual machines or Android runtime emulators.

Technical Architecture & Implementation

Low-level system shim bridging Android Bionic libc to Linux glibc:

Binary Patching Engine: Patches proprietary shared libraries with custom DT_VERNEED shims to resolve glibc ABI incompatibilities.
Camera Stream Pipeline: Feeds real-time direct V4L2 video captures into proprietary vision inferencing cores on Linux without JVM or emulator layers.

Bionic-to-glibc shim · DT_VERNEED patching · Direct V4L2 streaming

C++ Linux APIs V4L2 Jetson Orin

Jerome Antony Robin

Open Source Silicon & Digital Design Researcher

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