Edge AI & Embedded Vision Intern · Chennai, India
- Engineered a container-free native Linux runtime port of Google’s mobile vision engine for x86_64 and ARM64 via a custom Bionic-to-glibc translation shim.
- Developed high-throughput, zero-copy C++ and Python SDKs interfacing multi-camera V4L2 video streams directly with embedded neural network backends.
- Trained, pruned, and fine-tuned edge vision models using PyTorch; executed post-training quantization (INT8/FP16) and deployed optimized pipelines across TensorRT for NVIDIA Jetson and TFLite for edge devices.
Research Intern (FPGA & Systems) · Chennai, India
- Developed custom hardware accelerators and compute pipelines using Verilog, VHDL, and Vivado HLS across Xilinx Zynq and Microchip PolarFire FPGA architectures.
- Ran cycle-accurate RTL verification, testbench simulation, and corner-case functional debug using Vivado, GHDL, and ModelSim.
- Integrated and evaluated on-chip bus interconnects and protocols, handling AXI4-Lite, AXI-Stream, AXI-DMA, and Wishbone interfaces.
- Built bare-metal C/C++ runtimes and TFLite Micro inference engines on ARM Cortex-M microcontrollers, implementing static memory arena management.
- Performed physical board-level validation, timing debug, and hardware-software co-design using logic analyzers, /dev/mem drivers, and Linux interfaces.
Lead Developer & Architect · Open Source
- Architected Silis to democratize custom silicon design, rejecting fragmented proprietary monoliths in favor of an open, deterministic RTL-to-GDSII workbench that makes physical IC design accessible to beginners.
- Unified open-source synthesis, place-and-route, timing analysis, and DRC/GDS engines into an automated execution plane using CMake, modern C++, PyQt6, and Python.
- Engineered native C++ backend engines bound via pybind11 for sub-millisecond physical layout DEF parsing, 60 FPS graphical rendering using OpenGL, and live static timing analysis clock-tree visualizers.